1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns a method of planarizing the surfaces of a wafer using chemical mechanical polishing.
2. Description of the Related Art
Integrated circuits are typically comprised of a plurality of semiconductor devices formed in or on a substrate. In current applications, integrated circuits can consist of literally thousands or millions of individual semiconductor devices formed in or on the substrate. Typically, large numbers of integrated circuits are formed on a single wafer by selectively exposing regions of the wafer so as to allow for deposition or implantation of impurities into a semiconductor wafer to thereby alter the characteristics of the wafer to produce the desired different semiconductor devices. The semiconductor devices can be formed in the exposed regions of the wafer using well-known masking techniques in conjunction with well-known diffusion, implantation or deposition techniques. Over the past several decades, the scale of integration of integrated circuits has increased.
More particularly, semiconductor device fabrication techniques have been developed which allow for a higher density of semiconductor devices to be formed in the integrated circuit. As the scale of integration has increased and as the size of the individual semiconductor devices has decreased, it has become more important that integrated circuit designers and fabricators consider the structural integrity of the deposited devices and of the integrated circuit as a whole.
Repeated deposition of materials into the exposed regions of the wafer can result in the integrated circuit having a non-planar upper surface. As the upper surface of the integrated device becomes less planar, the ability to form additional semiconductor devices on the integrated circuit becomes more difficult. Moreover, the existence of protrusions in the topography of the integrated circuit affects the structural integrity of the circuit and can result in failure of the device. Consequently, integrated circuit designers and fabricators have increasingly used planarization techniques to planarize the upper surface of the integrated circuits during fabrication.
One particular planarization technique is known as chemical mechanical polishing or planarization (CMP). CMP is a technique whereby the upper surface of a wafer is globally planarized by simultaneously abrasively polishing and etching the upper surface of the wafer. Basically, the wafer is positioned adjacent a pad that is moved with respect to the wafer and the pad, and a slurry which is typically comprised of an etchant liquid. An abrasive encapsulated within a suspension fluid is introduced into the interface between the slurry and the pad. The pad is then applied to the wafer so that protrusions in the surface topography of the integrated circuits on the wafer can be removed by a combination of abrasive polishing and etching to thereby planarize and polish the upper surface of the wafer. As CMP is removing protruding layers, it is desirable to be able to stop the CMP process after the layers have been removed without damaging or removing too much of the underlying layers. Typically, various process parameters are analyzed in order to determine whether a predefined end point, indicating that a particular layer has been removed, has occurred. Hence, the process parameters are analyzed to determine whether an end point corresponding to the removal of a desired layer has occurred such that the CMP process can be stopped before excessive removal or damage of underlying layers occurs.
Presently, there are a number of different process parameters and techniques for determining end points of a CMP process. One simple technique is to analyze the current that is being drawn by the motors that are rotating the pad and the wafer. Oftentimes, the layer to be removed is more easily removed than an underlying layer such that when the pad reaches the underlying layer, the frictional engagement between the pad and the wafer increases, which causes an increase in the current that is being drawn by the motors. Another more sophisticated technique of detecting an end point of a CMP process is to shine one or more light sources, such as lasers, through a window formed in the polishing pad so that laser light reflects off of the surface of the wafer. The light sources preferably have wavelengths selected so that the intensity of the reflected light increases dramatically when the CMP process exposes the underlying layer. This type of laser-based end point technology is currently used in products available from Applied Materials, Inc. of Santa Clara, Calif. While this type of technology is useful for detecting end points, the CMP process often introduces false peaks in the intensity which can be interpreted incorrectly by the CMP processing technology as the actual desired end point for terminating the CMP process.
In particular, it is believed that the slurry used in the CMP process may polish particular regions of the wafer more quickly than other regions of the wafer. If the light source reflects off of one of these over-polished regions of the wafer, the intensity of the reflected light may increase thereby causing the CMP assembly to halt the CMP process. Subsequent evaluation may require additional polishing of the wafer which introduces inefficiencies into the manufacturing process. For example, when the CMP process is stopped, the wafer is then sent to a buffing and cleaning station before it is evaluated. If the evaluation determines that the wafer has been under-polished, i.e., the upper layer has been only partially removed, the CMP process must be restarted from an unknown starting point which tends to lead to over-polishing and possible scratching of the wafer. Moreover, as any evaluation must occur following buffing and cleaning, these steps can complicate and add expense to the manufacturing process.
To avoid these problems, the CMP assembly may be set up with thresholds that are selected to avoid under-polishing of the wafer. However, increasing the thresholds can result in over-polishing of the underlying layer. Over-polishing can result in the underlying layer being excessively thinned or scratched. Further, the underlying layer may be grown to a greater thickness to accommodate thinning of the layer occurring as a result of the over-polishing of the wafer during the CMP process. However, as the scale of integration of integrated circuits increases, there is a need to be able to form layers to more precise tolerances which is hindered by the need to form oversized layers to accommodate thinning during the CMP process.
While these problems of accurate end point detection have been described in conjunction with light-based end point detection systems, it will be appreciated that under-polishing and over-polishing problems stemming from less accurate end point detection also occur in most, if not all, end point detection systems. Hence, there is a need for a system or process whereby end point detection during the CMP process can be improved. In particular, there is a need for a process or system which enables a more accurate assessment of when a particular layer has been removed by the CMP process to thereby enable halting of the CMP process before significant CMP has occurred on an underlying layer.